Why is my Cyclone V or Stratix V Altera_PLL reset port is inverted in simulation?

To work around this problem in ModelSim, add the following switch to the vlog command

define POSTFIT_SIM_USE_ICD_PLL_MODEL

For example add the following lines to the *_run_msim_gate_verilog.do file

For Cyclone V designs

vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/mentor/cyclonev_*.v
vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/cyclonev_atoms.v
vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL

For Stratix V designs

vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/mentor/stratixv_*.v
vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/stratixv_atoms.v
vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL

<QuartusII_installation_path>/quartus/eda/sim_lib/altera_primitives.v
vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/altera_lnsim.sv
vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/220model.v
vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/sgate.v
vlog define POSTFIT_SIM_USE_ICD_PLL_MODEL <QuartusII_installation_path>/quartus/eda/sim_lib/altera_mf.v
vsim  -t 1ps transport_int_delays transport_path_delays -voptargs= acc gate_work.<top_level_design.vho/vo>