You will encounter this synthesis error if you connect a PLL and ALTLVDS_RX megafunction in External PLL mode, and PLL clock switchover is enabled. This error occurs because the Quartus® II software does not insert a cyclonev_pll_lvds_output atom between the PLL and the ALTLVDS_RX megafunction during synthesis.
The workaround is to insert the following atom between the PLL and the LVDS_RX:
cyclonev_pll_lvds_output #(
.pll_loaden_enable_disable("true"),
.pll_lvdsclk_enable_disable("true")
) stratixv_pll_lvds_output_inst (
.ccout({loaden_from_pll, fclk_from_pll}),
.loaden(loaden_to_lvds),
.lvdsclk(fclk_to_lvds)
);
If the target is a Stratix® V device, you can change the name to stratixv_pll_lvds_output.
This is scheduled to be fixed in a future version of the Quartus II software.