Yes due to a bug in Quartus II Software Versions 10.1SP1 and earlier, channel 3 of a transceiver block may fail to function correctly after dynamic reconfiguration in Cyclone IV GX devices.
The failure symptoms are
- rx_freqlocked may be stuck in a deasserted (low) state when using the CDR in Automatic lock mode
- Receiver data errors and Rate Match FIFO overflow or underflow may be observed when using the CDR in manual lock mode
- Receiver data errors and an incorrect rx_clkout frequency may be observed when using the CDR in manual lock mode
- Transceiver-FPGA fabric interface output clocks may not toggle
Affected transceiver configurations in Quartus II Software Version 10.1SP1 and earlier are detailed below.
Configuration 1 detailed below may exhibit failure symptoms 1, 2, or 3
- Channel Reconfiguration mode is used AND
- Channel 3 and channel 0 in the same transceiver block are instantiated in a single ALTGX instance AND
- The bottom PLL is clocking the single ALTGX instance and top PLL is clocking other circuitry
Configuration 2 detailed below may exhibit failure symptom 4
- Channel Reconfiguration mode is used AND
- Channel 3 and any other channel in the same transceiver block are instantiated in a single ALTGX instance AND
- Top PLL is clocking the single ALTGX instance
To fix this issue install the appropriate patch, regenerate the altgx_reconfig MegaWizard, and fully recompile the design.
Patch 0.36 for Quartus II Software version 10.1
- PC patch 0.36 for Quartus II Software version 10.1
- Linux patch 0.36 for Quartus II Software version 10.1
- Readme file for patch 0.36 for Quartus II Software version 10.1
Patch 1.03 for Quartus II software version 10.1SP1
- PC patch 1.03 for Quartus II Software version 10.1SP1
- Linux patch 1.03 for Quartus II Software version 10.1SP1
- Readme file for patch 1.03 for Quartus II Software version 10.1SP1
This issue will be fixed in a future version of the Quartus II software.