Description
Yes. The DCLK signal, which is the configuration clock signal in Passive Serial, Fast Passive Parallel and Passive Parallel Synchronous modes, can toggle before and after configuration.
Toggling DCLK at the beginning of configuration should not be an issue if the DATA signal is held high or low. FPGAs look for a startup sequence on the DATA lines, before they start registering configuration data. So as long as the DATA signal is not toggling randomly, DCLK transitions will not initiate the configuration cycle or cause errors.
After configuration, the input on DCLK is ignored by the FPGA.