DDR2 and DDR3 SDRAM Controller with UniPHY User Guide Contains Imprecise Clock Information

The Phase and Clock Network Type columns of tables 6-1 and 6-2 in the user guide. contain generalized clock phase and network type information that may not be. applicable to your design. In reality, clock phase and network type are dependent on both the target device type and the specific parameterization of your particular IP. core.

The workaround to determine correct clock phase is to run the TimeQuest Timing Analyzer and consult the Clocks Summary report. The workaround to determine� clock network type is to consult the Quartus Settings File (.qsf) for your design.