In Stratix® II and Stratix II GX devices, each fast PLL can drive up to 25 altlvds receiver channels when using DPA. Each center fast PLL can drive up to 25 altlvds receiver channels in each adjacent bank for a total of up to 50 channels. The requirement is that all of the DPA receiver channels must be within 25 LAB-rows of each other per bank. Not all devices can support 25 DPA channels driven by a center fast PLL, it depends on the layout of the particular device used.
You may find a case where you know your device can support a given number of DPA channels, yet Quartus® II software may issue an error during the compilation process which states you have exceeded the number of DPA receivers available in your device. For example, the EP2SGX130GF1508 device has 48 channels which can be driven by either of the center fast PLLs. (Once one center fast PLL is used to drive receivers in both banks, the other center fast PLL cannot be used to drive receivers). If you set the number of channels in the altlvds_rx MegaWizard® to 48, you may get a compilation error due to the way the Quartus II software places your pins if no pin locations are assigned.
There are two types of dedicated input clock pins on the Stratix II and Stratix II GX side banks, one is strictly a dedicated clock input which can drive the PLLs. The other type is a dual purpose pin - it can be used as either a dedicated clock input pin for the PLLs or it can be used as a SERDES receiver. If the Quartus II fitter places the PLL input clock on one of the dual purpose pins, you will lose one of your receiver channels and receive a no fit error.
To avoid this error, you can make a pin assignment to the clock pin to place it on the dedicated input pin that does not have the SERDES circuitry. This will allow you to have the maximum possible number of DPA receiver channels available for your design.
The following describes the dedicated clock pins available in I/O banks 1 and 2 in Stratix II and Stratix II GX devices:
CLK0p, CLK2p: Dedicated input clock pins with SERDES receivers.
CLK1p, CLK3p: Dedicated input clock pins without SERDES receivers.
The following describes the dedicated clock pins available in I/O banks 5 and 6 in Stratix II devices:
CLK8p, CLK10p: Dedicated input clock pins with SERDES receivers.
CLK9p, CLK11p: Dedicated input clock pins without SERDES receivers.
All FPLL[10..7]CLKp pins do not have SERDES receivers, these are the dedicated clock input pins for the corner fast PLLs (not available in all devices).
Please note, differential on chip termination is only supported on the dual purpose dedicated clock input pins that also have SERDES receivers. The dedicated input clock pins that do not have SERDES receivers do not support differential on chip termination, external resistors are required.