Article ID: 000075762 Content Type: Troubleshooting Last Reviewed: 10/23/2013

Arria® V Device Family Pin Connection Guidelines: Known Issues



Issue 160236: Version 1.9

For the BOOTSEL (BSEL) and CLOCKSEL (CSEL) pins it shows that a 4.7K-ohm to 10K-ohm pull-up resister can be used but does not specify the voltage the pull-up resistor should be tied to.

The pull-up resistors for the BSEL and CSEL pins should be tied to the VCCIO of the banks that contain those pins.

Issue 63747: Version 1.3

DCLK is not listed as a dual purpose pin.  DCLK can be configured to be a user I/O pin after configuration when the configuration mode is an Active mode.

Issue 44313: Version 1.1

The connection guideline for unused GXB_RX pins says to connect to GND through a 10-k. resistor.  The 10-k. resistor is un-necessary, unused GXB_RX pins can be tied directly to GND.

Issue 27900: Version 1.1

The CLK[0:23][p,n] Pin Type, Pin Description, and Connection Guidelines are not correct.  These are dual purpose I/O pins with output buffer capability.  The following describes the CLK[0:23][p,n] pins: 

Pin Type: "Input" should change to "I/O".

Pin Description: "Dedicated positive and negative clock input pins that can also be used as I/O pins.  OCT Rd is supported when used as differential input.  OCT Rt is supported when used as SSTL or HSTL input.  OCT Rs is supported for output operations.

When using single-ended I/O standard, only the CLK[0:23]p pins serve as the dedicated input pins to the PLL."

Connection Guidelines: "These pins can be tied to GND or left unconnected.  If unconnected, use Quartus II software programmable options to internally bias these pins.  They can be reserved as input tristate with weak pull up resistor enabled, or as outputs driving GND."

Related Products

This article applies to 4 products

Arria® V SX SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA