Article ID: 000075705 Content Type: Troubleshooting Last Reviewed: 06/08/2015

Why do I see excessive receiver latency when using the Low Latency or Native PHY, 10G PCS Basic mode on Stratix V GX or Arria V GZ devices?

Environment

    Quartus® II Subscription Edition
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Description

You may see excessive receiver latency when using the Low Latency or Native PHY, 10G PCS Basic mode on Stratix® V GX or Arria® V GZ devices under the following conditions:

  • Bit Slip is selected as the Word Alignment mode
  • The gearbox ratios are configured for 66:40, 64:32, or 50:40

For the transceiver PHY configurations above, the round-trip loopback latency may increase by 1-23 additional parallel clock cycles if the rx_bitslip port is toggled more than FPGA fabric interface width -1 times.

Resolution

To work around this problem, you should not toggle the rx_bitslip port more than FPGA fabric interface width -1 times for the transceiver PHY configurations above.

 

Altera recommends separating rx_bitslip pulses by at least 20 parallel clock cycles to account for transceiver PCS pipeline latency.

 

An alternative workaround is to use the rx_clkslip function on the Native PHY.

Related Products

This article applies to 4 products

Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA
Arria® V GZ FPGA

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