Article ID: 000075655 Content Type: Troubleshooting Last Reviewed: 09/12/2012

Why does the Quartus II software reports minimum pulse width violations for the 40Gb/100Gb Ethernet MAC and PHY Example Design?

Environment

    Quartus® II Subscription Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description Due to a bug of the Quartus® II software version 12.0 and 12.0SP1, the minimum pulse width violations are reported.
Resolution The minimum pulse width violations can be safely ignored with the Quartus II software version 12.0 and 12.0SP1. This issue is fixed in version 12.0SP1.

Related Products

This article applies to 3 products

Stratix® V GX FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.