When using the ALTTEMP_SENSE megafunction, you must ensure the clock that is applied to the IP is less than or equal to 1.0MHz. When using a higher frequency clock, the megafunction allows you to choose a divide by 40 or divide by 80 factor to reduce the clock frequency to be less than or equal to 1.0MHz.
However, the TimeQuest timing analyzer may issue a minimum pulsewidth violation when using the clock divider factor of 80. When either of the divide factors are used, the TimeQuest timing analyzer will only analyze the clock for the divide by 40 selection. Thus, if you have an input clock that is greater than 40MHz, and select the divide by 80 option, the TimeQuest timing analyzer will calculate the input clock frequency to the ALTTEMP_SENSE megafunction will be greater than 1.0MHz.
You can add a Synopsys Design Constraint (SDC) to override the incorrect clock frequency calculation. The following example constraint is based on output CLK0 from an ALTPLL megafunction (inst3) driving the CLK input port of the ALTTEMP_SENSE megafunction (inst5).
create_generated_clock -name {inst5|tsdadc_alttemp_sense_vps_component|sd1|clk} \
-source [get_pins {inst3|altpll_component|auto_generated|pll1|clk[0]}] \
-divide_by 80 -multiply_by 1 -duty_cycle 50.00 \
[get_pins { inst5|tsdadc_alttemp_sense_vps_component|sd1|clk } ]
This will be fixed in a future version of the Quartus® II software.