Article ID: 000075635 Content Type: Product Information & Documentation Last Reviewed: 01/09/2023

How do I access the Intel® Stratix® 10 PCI Express* configuration space registers through the Hard IP reconfiguration interface ?

Environment

    PCI Express
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Description

Do the following steps to access the PCIe* configuration space registers through the Hard IP reconfiguration interface.

 

     

    Resolution

    1. Enable the "Enable hard IP dynamic reconfiguration of PCIe read-only registers" parameter in the Configuration, Debug, and Extension Options tab in the IP Catalog of Intel® Stratix® 10 PCI Express* Hard IP.

    2. Access through the Hard IP reconfiguration interface whose signals are hip_reconfig_*

    • When indicating PCIe configuration space, the hip_reconfig_address[20] should be set to 1'b1.
    • The hip_reconfig_address[11:0] provides full byte access to the 4 Kbytes PCIe configuration space.
    • For the address map of the PCIe configuration space registers, refer to the Configuration Space Registers section in the Registers chapter of the Intel Stratix 10 PCI Express IP User Guide.

     

    Related Products

    This article applies to 3 products

    Intel® Stratix® 10 GX FPGA
    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 SX SoC FPGA

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