Why cant I use the Intel® Quartus® Prime Transceiver Toolkit with the Intel Interlaken (2nd Generation) for Intel FPGA IP Design Example on Intel Stratix® 10 devices?

Due to a problem in the Intel Interlaken (2nd Generation) for Intel FPGA IP Design Example generated in the Intel® Quartus® Prime Pro Edition Software version 21.1, the mgmt_clk signal has a virtual pin assignment which prevents the Transceiver Toolkit from being assigned to a device pin.

To fix this problem, open the Quartus Settings File (.qsf) of the Intel Interlaken (2nd Generation) for Intel FPGA IP Design Example, and replace the following virtual pin assignment with an assignment to a 100MHz clock signal on your PCB.

Replace this assignment.

set_instance_assignment -name VIRTUAL_PIN ON -to mgmt_clk

You should also ensure that you tick the  “Enable Native PHY Debug Master Endpoint (NPDME)” option when generating the Intel Interlaken (2nd Generation) for Intel FPGA IP Design Example.

This problem is fixed starting with the Intel® Quartus® Prime Pro/Standard Edition Software version 21.3.