Article ID: 000075616 Content Type: Error Messages Last Reviewed: 07/31/2017

Error(13381): Verilog HDL error at alt_vip_cps_alg_core_packer.sv(169): part-select has negative or zero size, but must use one or more bits

Environment

    Intel® Quartus® Prime Pro Edition
    DSP
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

Due to a problem with the Arria® 10 Color Plane Sequencer II IP core, you may see the above error in Quartus® Prime Pro software version 16.1 when compling the IP with a parameterization that uses more than one pixel in parallel.

Resolution

This problem has been fixed starting in software version 16.1.1 of the Quartus Prime Pro software.

Related Products

This article applies to 1 products

Intel® Arria® 10 FPGAs and SoC FPGAs

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