Article ID: 000075606 Content Type: Troubleshooting Last Reviewed: 07/20/2015

Why can't I use the x1 line to clock Arria V device transceiver channels higher than 6.5536 Gbps within a transceiver bank but across a triplet boundary when using Quartus II software version 15.0.1 and earlier?

Environment

  • Arria® V GT FPGA
  • Arria® V GX FPGA
  • Arria® V ST SoC FPGA
  • Arria® V SX SoC FPGA
  • Clock
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    Description

    Due to a bug in Quartus® II software version 15.0 Update 1 and earlier, the Fitter will prevent you from clocking Arria® V device transceiver channels higher than 6.5536 Gbps within a transceiver bank but across a triplet boundary.

    Resolution

    To work around this problem, you can install the Quartus II software version 15.0 Update 1 and then download and install patch 1.07 from the links below.

    This problem is scheduled to be fixed in a future version of the Quartus II software.

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