Why does the HDMI Intel® FPGA Source IP encounter intermittent HDMI 2.1 Tx link training failure after hotplug or reset operation ?

Due to a problem starting in version 19.4 of the Intel® Quartus® Prime Pro software when using the Intel® Arria® 10 Devices, and version 20.4 of the Intel® Quartus® Prime Pro software when using the Intel® Stratix® 10 devices, the HDMI Intel® FPGA Source IP core may intermittently encounter HDMI 2.1 Tx link training failure after hotplug or reset operation.

This problem is due to the HDMI Intel® FPGA Source IP core not monitoring and clearing the HDMI 2.1 link training FLT_update status flag on the destination HDMI Sink receiver.

This problem is fixed starting from the Intel® Quartus® Prime Pro Edition version 21.1 software.