Due to a problem in the Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Gen3 configuration, Setup violations will be seen when enabling the Debug Toolkit and configuring the IP for Gen3 modes.
These timing violations can be safely ignored.
To work around this problem, include the following set_false_path constraints to remove the timing violations on your project:
For Gen3/4x16:
set_false_path -from *|maib_and_tile|hdpldadapt_rx_chnl_10~pld_rx_clk1_dcm.reg* -to *|toolkit_inst|ptile_link_insp|avmm_readdata_r*
set_false_path -from *|maib_and_tile|hdpldadapt_rx_chnl_10~pld_rx_clk1_dcm.reg* -to *|toolkit_inst|toolkit_readdata*
For Gen3/4x8:
set_false_path -from *|maib_and_tile|hdpldadapt_rx_chnl_10~pld_rx_clk1_dcm.reg* -to *|toolkit_inst|ptile_link_insp|avmm_readdata_r*
set_false_path -from *|maib_and_tile|hdpldadapt_rx_chnl_11~pld_rx_clk1_dcm.reg* -to *|toolkit_inst|ptile_link_insp|avmm_readdata_r*
set_false_path -from *|maib_and_tile|hdpldadapt_rx_chnl_10~pld_rx_clk1_dcm.reg* -to *|toolkit_inst|toolkit_readdata*
set_false_path -from *|maib_and_tile|hdpldadapt_rx_chnl_11~pld_rx_clk1_dcm.reg* -to *|toolkit_inst|toolkit_readdata*
For Gen3/4x4:
set_false_path -from *|maib_and_tile|hdpldadapt_rx_chnl_10~pld_rx_clk1_dcm.reg* -to *|toolkit_inst|ptile_link_insp|avmm_readdata_r*
set_false_path -from *|maib_and_tile|hdpldadapt_rx_chnl_11~pld_rx_clk1_dcm.reg* -to *|toolkit_inst|ptile_link_insp|avmm_readdata_r*
set_false_path -from *|rx_deskew|u_wrpcie_deskew_0_5_port2|u_wrpcie_deskew|dpchannels[4].tx_aib_deskew_datapipe|o_aib_data_deskewed* -to *|toolkit_inst|ptile_link_insp|avmm_readdata_r*
set_false_path -from *|rx_deskew|u_wrpcie_deskew_0_5_port3|u_wrpcie_deskew|dpchannels[4].tx_aib_deskew_datapipe|o_aib_data_deskewed* -to *|toolkit_inst|ptile_link_insp|avmm_readdata_r*
set_false_path -from *|maib_and_tile|hdpldadapt_rx_chnl_10~pld_rx_clk1_dcm.reg* -to *|toolkit_inst|toolkit_readdata*
set_false_path -from *|maib_and_tile|hdpldadapt_rx_chnl_11~pld_rx_clk1_dcm.reg* -to *|toolkit_inst|toolkit_readdata*
set_false_path -from *|rx_deskew|u_wrpcie_deskew_0_5_port2|u_wrpcie_deskew|dpchannels[4].tx_aib_deskew_datapipe|o_aib_data_deskewed* -to *|toolkit_inst|toolkit_readdata*
set_false_path -from *|rx_deskew|u_wrpcie_deskew_0_5_port3|u_wrpcie_deskew|dpchannels[4].tx_aib_deskew_datapipe|o_aib_data_deskewed* -to *|toolkit_inst|toolkit_readdata*