Article ID: 000075503 Content Type: Product Information & Documentation Last Reviewed: 02/07/2014

How should I place the QDRII/QDRII mem_cq and mem_cq_n pins in Arria V GX/GT/ST/SX devices?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    From the device pinout file, there is only one pin location available for both mem_cq and mem_cq_n pins. For these Arria V devices complementary strobes are not supported, so only one of the mem_cq or mem_cq_n pins will be used depending on the read latency setting.

     

    Resolution

    Related Products

    This article applies to 10 products

    Arria® V GZ FPGA
    Arria® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA
    Cyclone® V GX FPGA
    Arria® V ST SoC FPGA
    Arria® V GX FPGA
    Arria® V GT FPGA
    Cyclone® V E FPGA
    Cyclone® V SE SoC FPGA

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