Why does the HDMI Intel® FPGA IP encounter audio failure in HDMI audio packet layout 1 configuration?

Due to a problem starting in version 14.0 of the Intel® Quartus® software, the HDMI Intel® FPGA IP may encounter audio failure in HDMI audio packet layout 1 configuration.

This is due to the HDMI Intel® FPGA Source IP is expecting continuous audio channel allocation only while CTA-861 specification allows for discontinuous audio channel allocation.

• For instance in 4 channel audio mode,  audio data packet sent through audio channel 1, 2, 3 and 5 (skipping audio channel 4) is a valid configuration but the HDMI Intel® FPGA Source IP will interpret it as missing audio data packet scenario 

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 21.2.