Article ID: 000075419 Content Type: Error Messages Last Reviewed: 10/10/2018

Warning (16817): Verilog HDL waring at alt_etipc3_nphy_elane.v (12698)

Environment

  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Quartus® Prime Pro Edition
  • 25G Ethernet Intel® FPGA IP
  • Low Latency 100G Ethernet Intel® FPGA IP for Arria® 10 and Stratix® V
  • Ethernet 10G MAC Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    You may see the warning shown above due to module collision when compiling a design with multiple instances of the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel FPGA IP.

    When multiple instances of the E-tile Hard IP for Ethernet Intel FPGA IP are used with different configurations within the same Intel® Quartus® Prime project, the design can compile incorrectly which can also cause fitter errors.

    Users will see compilation warnings where settings for modules with the same name are overwritten in both Intel Quartus Prime compilation and during simulation compilation.

    Resolution

    This problem is scheduled to be fixed in a future release of the Intel Quartus Prime software.

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.