Due to a problem in the Low Latency 40- and 100-Gbps Ethernet IP Core, the rx_pcs_ready signal from the core sometimes is stuck deasserted at start-up. This problem means the RX PCS block does not come up properly. The symptom sometimes disappears if the FPGA is reconfigured.
The problem is on hardware only and does not show up in simulation. This is a start-up only problem. Once rx_pcs_ready is high, the Ethernet IP Core works properly.
To work around this problem you can recompile the Quartus® Prime project with a different timing seed. The chance of running into this problem with a different seed is low.
The problem is fixed beginning with the Quartus Prime software version 16.1 update 2.