Article ID: 000075401 Content Type: Error Messages Last Reviewed: 09/19/2017

Error(19300): DSP WYSIWYG primitive "dafloater_i|s10fpdsp_block_0|sp_mult" has clock setting "adder_input_clock" that is not set to "none".

Environment

    Intel® Quartus® Prime Pro Edition
    DSP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem with the Stratix® 10 Native Floating Point DSP IP in Quartus® Prime Pro software version 17.1 Stratix 10 ES Edition, you may observe the above error during compilation if you are using the multiplication mode.

Resolution

Do the following changes in the <ip_file_name>_altera_s10fpdsp_block_160_mdhrmmi.sv:

from

   .adder_input_clock("0")     //(line 28)

to

   .adder_input_clock("NONE")

 

This problem is fixed starting in Quartus Prime Pro v17.1 release software.

Related Products

This article applies to 1 products

Intel® Stratix® 10 FPGAs and SoC FPGAs

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