Article ID: 000075384 Content Type: Troubleshooting Last Reviewed: 07/25/2017

Why does my Arria 10 PCIe Hard IP link width downtrain?


  • Intel® Arria® 10 SX SoC FPGA
  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Arria® 10 GT FPGA
  • Intel® Arria® 10 GX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express

    Critical Issue


    When the Intel® Arria® 10 PCIe* Hard IP core receives TS2 training sequences during the Polling.Config state, automatic lane polarity inversion is not guaranteed. The link may train to a smaller than expected link width or may not train successfully. For example, a PCIe x8 link may train to x4. This can affect configurations with any PCIe speed and width.

    Automatic lane polarity inversion is supported when the Arria 10 PCIe Hard IP receives TS1 training sequences during the Polling.Active state. 


    For closed systems where you control both ends of the PCIe link, design the board without lane polarity inversion between the Arria 10 PCIe Hard IP and the link partner. If the board design is already finalized with lane polarity inversion, then file a Service Request through mySupport for further instructions.

    For open systems where you do not control both ends of the PCIe link, there will be an option for a lane polarity inversion soft IP workaround in a future version of the Quartus® Prime software. File a Service Request through mySupport if this IP is needed earlier. This soft IP does not support Gen1x1 Arria 10 PCIe Hard IP configuration, Configuration via Protocol, or Autonomous Hard IP mode. 



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