Article ID: 000075368 Content Type: Troubleshooting Last Reviewed: 03/28/2017

Are there any problems in the VHDL variant of the 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core for Arria V or Arria 10 devices?

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Arria® V FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • 1G 2.5G 5G 10G Multi-rate Ethernet PHY Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Yes, if you instantiate the 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core for Arria® V or Arria 10 devices within a VHDL generate block, there is a timing constraints file (.sdc) problem. The timing constraints provided by the IP Core are invalid, and proper timing analysis will not be performed.

    Resolution

    To work around this problem, do not use a VHDL generate block to instantiate the IP Core.

    This problem is scheduled to be fixed in a future release of the Quartus® Prime software.

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