Critical Issue
Description
Yes, if you instantiate the 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core for Arria® V or Arria® 10 devices within a VHDL generate a block, there is a timing constraints file (.sdc) problem.
The timing constraints provided by the IP Core are invalid, and proper timing analysis will not be performed.
Resolution
To work around this problem, do not use a VHDL generate block to instantiate the IP Core.
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Software.