Article ID: 000075359 Content Type: Troubleshooting Last Reviewed: 04/06/2017

RapidIO II Simulation testbench failure when parameter "Enable Transceiver control and status register" is enabled.

Environment

    Intel® Quartus® Prime Pro Edition
    RapidIO II (IDLE2 up to 6.25 Gbaud) Intel® FPGA IP
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Critical Issue

Description

For Arria® 10 and Stratix® 10 families. When RapidIO II IP Core is generated with the optional parameter "Enable transceiver control and status register" enabled, the provided simulation testbench will fail. The failing behavior is that the transceiver does not exit from reset, and rx_is_lockedtodata does not assert.

Resolution

Advice is to run the simulation without enabling the parameter "Enable transceiver control and status register" if affected.

This problem has been fixed starting in Quartus® Prime software version 17.0.

Related Products

This article applies to 2 products

Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs

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