Article ID: 000075358 Content Type: Troubleshooting Last Reviewed: 06/19/2017

Why is app_int_ack status signal not available for PCI Express Hard IP Core of Cyclone V devices?

Environment

  • Cyclone® V FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Cyclone® V Hard IP for PCI Express Intel® FPGA IP
  • Avalon-MM Cyclone® V Hard IP for PCI Express Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    This status signal is not offered for Cyclone® V devices 

    Resolution

    To work around this issue, please refer to app_msi_ack status signal to indicate completion of app_int_sts_vec signal assertion and deassertion

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.