Article ID: 000075245 Content Type: Troubleshooting Last Reviewed: 02/10/2014

Why does my Cadence* NCSIM* Arria® V PCIe* simulation fail complete getting stuck in L0 and timeout?

Environment

  • Arria® V GZ FPGA
  • Arria® V SX SoC FPGA
  • Arria® V ST SoC FPGA
  • Arria® V GT FPGA
  • Arria® V GX FPGA
  • Quartus® II Subscription Edition
  • Arria® V Hard IP for PCI Express Intel® FPGA IP
  • Arria® V GZ Hard IP for PCI Express Intel® FPGA IP
  • Avalon-MM Arria® V Hard IP for PCI Express Intel® FPGA IP
  • Avalon-MM Arria® V GZ Hard IP for PCI Express Intel® FPGA IP
  • V-Series Avalon-MM DMA for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to an issue when simulating the Arria® V Hard IP for PCI* Express* using Cadence* NCSim*  in Quartus® II version 13.0SP1 the simulation models must be updated.

    Resolution

    The updated files can be found at NewArriaVModelFiles.zip and replace the existing files in location:

    <your Quartus version>\quartus\eda\sim_lib\cadence

    This problem has been fixed starting in Quartus® II version 14.0.

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