Article ID: 000075231 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does my Stratix IV GX or Stratix IV GT design configured in Basic (PMA-Direct) mode not meet timing even if the left/right PLLs is implemented.as recommended in the Stratix IV Handbook, stratix_iv_gx_ki, stratix_iv_gt_ki

Environment

  • Stratix® IV GX FPGA
  • Stratix® IV GT FPGA
  • Stratix® IV FPGAs
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The "Left/Right PLL Requirement in Basic (PMA Direct) Mode" section of the "Stratix IV Clocking" chapter in volume 2 of the Stratix IV Handbook,  specifies that use of the left/right PLL is required to meet timing between the FPGA fabric and the transmitter PMA interface for basic (PMA-Direct) configurations above some data rates. These left/right PLLs should be placed on the same side of the device to meet timing.

The Quartus® II software version 9.0 may incorrectly place these left/right PLLs on the other side of the device.

To ensure the Quartus II software places the left/right PLLs on the same side, use one of the following two options:

 

  • Specify the left/right PLL by location assignment
    1. Find the PLL output clock in the Assignment Editor.
      1. Open up the Assignment Editor by clicking on Assignment Editor from the Assignments menu
      2. Click on PLL in the Category window
      3. Double-click the blank field in the To column and click on the arrow on the right hand side to select Node Finder. 
      4. Locate and select the PLL output clock for your particular ALTPLL instance.
      5. Click OK to close the Node Finder.  The PLL output clock signal name is now  populated in the To column.
    2. Assign a particular phyisical PLL # to your PLL output clock by double-clicking in the Location column and selecting a particular PLL. You should select a PLL on the same side of the device as the transceiver channels. For example, select a right side PLL (for example - PLL_R4), if the associated transceiver channels are GXBR0, GXBR1, GXBR2, or GXBR3. 
  • Specify the left/right PLL by "edge" assignment
    1. Find the left/right PLL output clock in the Assignment Editor.
      1. Open up Assignment Editor by clicking on Assignment Editor from the Assignments menu.
      2. Click on Edge in the Category window
      3. Double-click the blank field in To column and click on the arrow on the right hand side to select Node Finder.
      4. Locate and select the PLL output clock for your particular ALTPLL instance
      5. Click OK to close the Node Finder. PLL output clock signal name should now be populated in To column.
    2. Assign a particular Edge to your PLL output clock by double-clicking in the Location column and selecting a particular Edge. Select the EDGE_LEFT option, if the associated transceiver channels are located on the left side of the device or select the EDGE_RIGHT option, if the associated transceiver channels are located on the right side of the device.

For verification, you can locate and confirm the physical location of the ALTPLL instances using the Quartus II Chip Planner, after the fitter process completes.

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