Article ID: 000075008 Content Type: Troubleshooting Last Reviewed: 02/13/2023

Why does CvP Update fail after accessing the SDM Mailbox IPs in Intel® Stratix® 10 devices?


  • Intel® Quartus® Prime Pro Edition
  • Altera S10 Mailbox Client Core
  • Temperature Sensor Intel® Stratix® 10 FPGA IP
  • Voltage Sensor Intel® Stratix® 10 FPGA IP

    Due to a known problem in Intel® Quartus® Prime Pro Edition Software version 18.1 Update 1 and later, a Configuration via Protocol (CvP) Update on Intel Stratix® 10 devices could  fail if access to either an Intel Stratix 10 Temperature Sensor  / Intel Stratix 10 Voltage Sensor / Chip ID Intel Stratix 10 FPGA IP core / Stratix 10 Serial Flash Mailbox Client Intel FPGA IP core is performed before the subsequent core configuration. 


    To work around this problem, either hold the SDM IP in reset for at least 1 second after the device enters user mode or remove the instance of the SDM IPs from your design. 


    See Related KDB

    Why does reconfiguration of Intel® Stratix® 10 devices fail with designs containing an instance of any of the SDM Mailbox IPs?


    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs