Article ID: 000075004 Content Type: Troubleshooting Last Reviewed: 01/21/2023

Why do some GPIO pins drive low during JIC programming in Cyclone® V SoC devices?


  • Intel® Quartus® Prime Lite Edition
  • Intel® Quartus® Prime Standard Edition

    Due to a problem in the factory default SFL image in the Intel® Quartus® Prime Software, some general purpose I/O (GPIO) pins drive low when programming a serial configuration device with JTAG indirect configuration file (.jic) in the following variants of Cyclone® V SoC devices:

    • Cyclone V SE - Member Code A5, Package F896 (31mm)
    • Cyclone V SX - Member Code C5, Package F896 (31mm)
    • Cyclone V ST - Member Code D5, Package F896 (31mm)

    To work around this problem, replace the original factory default SFL image for the affected devices with the corrected image by doing the following steps.

    1. Download the following file and unzip it.  You can find the corrected default SFL image, sfl_enhanced_01_02d120dd.sof.
    2. Open the directory factory default SFL images location.
      • Intel Quartus Prime Software  : <install directory>/quartus/common/devinfo/programmer
      • Stand-alone Intel Quartus Prime Software Programmer : <install directory>/qprogrammer/common/devinfo/programmer
    3. Find sfl_enhanced_01_02d120dd.sof in the directory and replace it with the corrected SFL image.

    Related Products

    This article applies to 3 products

    Cyclone® V SE SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA