Article ID: 000074947 Content Type: Troubleshooting Last Reviewed: 03/17/2023

Is it possible to dynamically enable or disable Global Clock (GCLK) or Regional clock (RCLK) networks that drive fPLLs in Stratix® V, Arria® V, or Cyclone® V devices?

Environment

  • Quartus® II Subscription Edition
  • PLL
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    No, it is not possible to dynamically enable or disable Global Clock (GCLK) or Regional clock  (RCLK) networks that drive fPLLs in Stratix® V, Arria® V, or Cyclone® V devices.

    However, due to a problem in the Quartus® II software version 13.1 and earlier, if you use the enable signal on a clock control block that drives an fPLL, compilation will not fail.

     

    Resolution

    Future versions of the Quartus II software are scheduled to generate an error/warning message when  you use the enable signal on a clock control block that drives an fPLL,

    Related Products

    This article applies to 15 products

    Stratix® V GT FPGA
    Stratix® V GS FPGA
    Arria® V GZ FPGA
    Arria® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V GX FPGA
    Cyclone® V E FPGA
    Stratix® V E FPGA
    Cyclone® V SE SoC FPGA
    Arria® V GT FPGA
    Cyclone® V SX SoC FPGA
    Cyclone® V GT FPGA
    Stratix® V GX FPGA
    Cyclone® V GX FPGA

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