Since version 2019.02.20. of Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines, the descriptions for the DEV_CLRn pin and the DEV_OE pin have been changed as follows:
- DEV_CLRn - Intel recommends you to tie the DEV_CLRn pin to GND when the Enable device-wide reset (DEV_CLRn) option is disabled and not used as an I/O pin.
- DEV_OE - Intel recommends you to tie the DEV_OE pin to GND when the Enable device-wide output enable (DEV_OE) option is disabled and not used as an I/O pin.
These changes have been done to simplify the pin connection guidelines for the DEV_CLRn pin and the DEV_OE pin to avoid confusion.
But you can also tie the DEV_CLRn pin and DEV_OE pin to VCCIO or leave these pins unconnected as long as the Enable device-wide reset (DEV_CLRn) option the Enable device-wide output enable (DEV_OE) option is disabled and not used as user I/O pins. When you leave the DEV_CLRn pin and the DEV_OE pin unconnected, setting these pins to input tri-state with weak pull-up is recommended.
Refer to the document, Intel® MAX® 10 FPGA Device Family Pin Connection Guidelines.