In the Intel® Quartus® Prime Pro Edition Software version 19.1, this error message may be seen in designs that target Intel Stratix® 10 devices that include one or more instances of the LVDS SERDES Intel FPGA IP. This error may be reported while Fitter or Timing Analyzer stages are being executed.
To work around this problem, make sure that the IOPLL Intel FPGA IP is listed before the LVDS SERDES Intel FPGA IP in the 'IP Components' tab on the Intel Quartus Project Navigator. Alternatively, you can go to Assignments > Settings… , then choose 'Timing Analyzer' category and re-arrange the order of the IP files.
Once the order of the IP files is correct, proceed to install the following patch for your operating system:
- Download Intel® Quartus® Prime 19.1 Pro Edition patch 0.19 for Windows (.exe)
- Download Intel® Quartus® Prime 19.1 Pro Edition patch 0.19 for Linux (.run)
- Download ReadMe file for the Intel® Quartus® Prime 19.1 Pro patch 0.19 (.txt)
This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 19.2.