Article ID: 000074892 Content Type: Troubleshooting Last Reviewed: 01/01/2015

Why does the SignalTap® II logic analyzer display incorrect data when the acquisition buffer is in Stratix® II M-RAM blocks?


  • Quartus® II Subscription Edition

    The SignalTap II logic analyzer may display corrupted data for Stratix II devices when the acquisition buffer is implemented in M-RAM blocks with the Quartus II software versions 4.1, 4.2, and 4.2 SP1 due to an issue with Stratix II M-RAMs as described in the Stratix II FPGA Family Errata Sheet.


    This problem is fixed in the Quartus II software beginning with version 5.0 because the acquisition buffer is not implemented in M-RAM blocks.

    In the Quartus II software version 4.1, 4.2, and 4.2 SP1, you can change the RAM type to M4K or M512 blocks in the SignalTap File (.stp) to implement the acquisition buffer outside of M-RAM blocks.

    Alternately, you can also install a patch for the Quartus II software version 4.2 SP1. Contact Altera® Applications for patch 1.13. Patch 0.13 is also available for the Quartus II software version 4.2, but Altera recommends upgrading to SP1 and then obtaining patch 1.13.

    Related Products

    This article applies to 1 products

    Stratix® II FPGAs