Article ID: 000074802 Content Type: Troubleshooting Last Reviewed: 06/20/2018

nPERSTL0 pin description update in Cyclone® 10 GX Pin Connection Guideline for PCIe* Hard IP


  • Intel® Quartus® Prime Pro Edition
  • ASMI Parallel Intel® FPGA IP

    Current Version: 2017.11.06

    Description: Connect this pin as defined in the Intel® Quartus® Prime software. This pin is powered by 1.8V supply and must be driven by 1.8V compatible I/O standards. Connect the PCIe* nPERST pin to a level translator to shift down the voltage from 3.3V LVTTL to 1.8V to interface with this pin. 

    Updated Guidelines:

    Description: When PCIe* nPERTL0 pin is not used for configuration purpose, user has option to select 1.2V/ 1.5V/ 1.8V compatible I/O standard. However, user must shift down the 3.3V LVTTL voltage from the PCIe* nPERST pin to the selected Cyclone® 10 GX nPERST I/O standard voltage level. Just ensure that you adhere to the VCCPGM to VCCIO restriction when using dual purpose configuration pins during configuration. For example, if your VCCPGM is 1.8V, your VCCIO has to be 1.8V according to PCG when dual purpose configuration pins are used.


    The information is scheduled to be updated in Pin Connection Guidelines in the future release of the document.

    Related Products

    This article applies to 1 products

    Intel® Cyclone® 10 GX FPGA