Article ID: 000074783 Content Type: Product Information & Documentation Last Reviewed: 04/22/2020

How do I set user-entered high speed tile usage in Intel® Arria®10 Early Power Estimator?


  • Intel® Quartus® Prime Pro Edition

    In Logic tab of current Intel® Arria®10 Early Power Estimator version 19.3, there are only three choices in drop down menu of High Speed Tile Usage setting when no CSV file imported:

    • Typical Design
    • Typical High Performance-Design
    • Atypical High-Performance design

    User defined value cannot be entered in these three options. In the design stage before CSV file is available, the 'Imported' option which custom value could be entered is required to be added in drop down menu.


    To work around this problem in Intel® Arria®10 EPE, follow the steps below:

    1. After download a new EPE file, export CSV in the main tab first;

    2. Open this exported CSV by note editor. Please pay attention here that you cannot open CSV file by Excel,  you must revise and save it in note editor. If you open and save CSV file by Excel, error will be reported in step5.

    3. Change the settings as below:

    Default settings:

        BLOCK,logic_high_speed_tile_usage_group,HSTileUsage,Typical Design,HSLABsImported,-1,HSMLABsImported,-1

    Updated setting example (Bold texts need to be adjusted for a given design, bold numbers are the absolute counts of LABs/MLABs):


    4. Save the txt file and Import the CSV  which already be revised to EPE;

    5. Then there will be imported option which corresponding 1062/287 labs usage in drop down menu of High-Speed Tile Usage of Logic tab.



    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs