Article ID: 000074671 Content Type: Troubleshooting Last Reviewed: 07/12/2019

Why does the Intel® Stratix® 10 MLAB RAM generate unknown output values in gate-level simulation with a VHDL netlist?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to a problem in the Intel® Stratix® 10 device simulation model in the Intel® Quartus® Prime Pro Edition software version 19.1 and earlier, you may see unknown (x) MLAB RAM output values in gate-level simulation with the VHDL netlist (*.vho). 

    Resolution

    To work around this problem, use the Verilog netlist (*.vo) for MLAB RAM in the gate-level simulation. 

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software. 

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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