Article ID: 000074643 Content Type: Troubleshooting Last Reviewed: 07/25/2023

Why do I see an efficiency issue when using the Arria® V and Cyclone® V hard memory controller with DQS tracking enabled?

Environment

    Intel® Quartus® Prime Standard Edition
    Intel® Quartus® Prime Lite Edition
    LPDDR2 SDRAM Controller with UniPHY Intel® FPGA IP
    DDR2 SDRAM Controller with UniPHY Intel® FPGA IP
    DDR3 SDRAM Controller with UniPHY Intel® FPGA IP
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Description

Arria® V and Cyclone® V DDR2,  DDR3/3L, and/or LPDDR2 designs with DQS tracking enabled may see reduced efficiency due to a long DQS tracking process where there is no periodic refresh being issued by the hard memory controller for a long period of time.

Resolution

Enable user auto-refresh options in the UniPHY IP.

Related Products

This article applies to 5 products

Arria® V GT FPGA
Cyclone® V FPGAs and SoC FPGAs
Arria® V GX FPGA
Arria® V ST SoC FPGA
Arria® V SX SoC FPGA

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