Article ID: 000074638 Content Type: Troubleshooting Last Reviewed: 02/05/2014

Low Latency Ethernet 10G MAC designs may fail timing in Arria 10 and Cyclone 10 GX devices

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Cyclone® 10 GX FPGA
  • Ethernet
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Large designs for Low Latency Ethernet 10G MAC using Arria® 10 and Cyclone® 10 devices may fail setup timing.

    Resolution

    To work around this issue, use Standard Fit compilation, and change the fitter seed number.

    This issue will be fixed in a future version of the Low Latency Ethernet 10G MAC.

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