How do I examine Intel® MAX® 10 FPGA on a Intel® Stratix®10 MX Development Kit?

When  Intel® Stratix® 10 MX FPGA is configured, examine for  Intel® MAX® 10 FPGA may not work. 

Set SW2 of the Development Kit to the following settings prior to scanning the JTAG with the Intel® Quartus® Prime Programmer.

This will enable user to access Intel® MAX® 10 FPGA reliably to examine the programmed data. 

Bit1: Open (OFF - On Board Intel® FPGA Download cable)

Bit2: Open (OFF - Intel® MAX®10 JTAG IN)

Bit3: Closed (ON - PCIe* Root Port JTAG OFF)

Bit4: Closed  (ON - Intel® Stratix® 10 MX JTAG OFF)

This setting will remove  Intel® Stratix ®10 from the JTAG, and examine will succeed.