Article ID: 000074567 Content Type: Troubleshooting Last Reviewed: 01/13/2023

Is there a known problem with how the Intel® Quartus® Prime Pro Edition Software implements Differential SSTL and HSTL I/O in Intel® Stratix® 10 devices?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Yes, due to a problem in the Intel® Quartus® Prime Pro Edition Software versions 17.0 or later, Differential SSTL and HSTL inputs might not sample the input signal when implemented on bi-directional I/O in Intel® Stratix® 10 devices if the respective VREF pin is not connected to a voltage reference. Differential SSTL and HSTL inputs should not require a VREF.

    Resolution

    This problem is fixed starting from the Intel® Quartus® Prime Pro Edition Software version 19.3.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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