Article ID: 000074539 Content Type: Troubleshooting Last Reviewed: 02/13/2023

Why does dynamic phase shift on Intel® Arria® 10 FPGA IOPLL output clocks fail sporadically?


  • Intel® Quartus® Prime Standard Edition
  • IOPLL Intel® FPGA IP
  • PLL Reconfig Intel® FPGA IP

    The dynamic phase shift feature might fail on the Intel® Arria® 10 FPGA IOPLL Intel® FPGA IP core in certain seed based compilations. This might happen if the advanced fitter options in the Intel® Quartus® Prime Software has Spectra Q Physical Synthesis enabled. You may expect to come across this problem if you are using the dynamic phase shift ports of the IOPLL or using the PLL Reconfig Intel FPGA IP core to perform the phase shift. This problem is isolated only to the dynamic reconfiguration logic of the IOPLL and does not affect any other part of the IP. 


    To work around this, set the Spectra Q Physical Synthesis setting to OFF for just the IOPLL Intel FPGA IP variation or for the entire design. This setting is OFF by default and can be found at :

    Assignments -> Settings -> Compiler Settings -> Advanced Fitter Settings -> Spectra Q Physical Synthesis. 

    This will be fixed in a future version of the Intel Quartus Prime Software.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs