Article ID: 000074528 Content Type: Troubleshooting Last Reviewed: 04/07/2017

Are there any known issues with the Altera PLL Reconfig IP for Arria 10, Stratix V, Arria V or Cyclone V devices which may cause reconfiguration to occasionally fail?

Environment

    Intel® Quartus® Prime Pro Edition
    PLL Reconfig Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Yes there is an issue with the Altera® PLL Reconfig IP for Arria® 10, Stratix® V, Arria V and Cyclone® V devices in Quartus® Prime software versions prior to 16.1,

In this IP there is a lack of synchronization of the locked signal, which is an asynchronous signal sourced from the PLL that is being reconfigured. This runs the small risk of causing a malfunction of the reconfiguration control state machine that the locked signal feeds, which operates in the mgmt_clk domain. This may result in a reconfiguration request to fail.

Resolution

This issue is fixed in Quartus Prime software version 16.1.

Related Products

This article applies to 4 products

Intel® Arria® 10 FPGAs and SoC FPGAs
Stratix® V FPGAs
Arria® V FPGAs and SoC FPGAs
Cyclone® V FPGAs and SoC FPGAs

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