The DMA controller master port data width may be narrower than expected if the component has not received the correct information on the width of the slaves attached from Qsys.
The DMA controller master ports (read_master and write_master) are dynamically sized to match the widest slave attached to the master. If the master port is connected to a bridge that is exported, the information on data width is not propagated to the DMA controller correctly.
In situations where the data width has not been propagated to the DMA controller component correctly, the data width may be overridden by creating a component which sets the data width correctly for Qsys, but has no effect on the functionality of the code.
An example of a bridge which can be used to set the DMA master port data width to 128-bits and the address width to 20-bits may be downloaded using these links:
You can use this example as a basis to create a different component that sets data width and address width to a value that you choose.
This problem is scheduled to be fixed in a future release of the Quartus® II software