Error(177020): The PLL reference clock was not placed in a dedicated input pin that can reach the fractional PLL

You may get this error message if you assign your input clock signal to a dedicated clock pin location and make a global clock (GCLK) assignment to this clock.

If the routing from the input clock pin to the PLL is not dedicated and uses the GCLK network, you need to add the ALTCLKCTRL mega function between the input clock pin and the PLL in your design to achieve a successful fit.

The error message is expected since the usage of non-dedicated routing from an input clock pin to a PLL is not recommended. The reason is that this could introduce jitter, and TimeQuest will not provide an accurate compensation delay figure.

This problem was fixed in Intel® Quartus® software version 13.1