Article ID: 000074478 Content Type: Error Messages Last Reviewed: 01/10/2014

Error(177020): The PLL reference clock was not placed in a dedicated input pin that can reach the fractional PLL

Environment

  • Quartus® II Subscription Edition
  • PLL
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description You may get this error message if you assign your input clock signal to a dedicated clock pin location and make a global clock (GCLK) assignment to this clock.
    Resolution

    If the routing from the input clock pin to the PLL is not dedicated and uses the GCLK network, you need to add the ALTCLKCTRL megafunction between the input clock pin and the PLL in your design to achieve a successful fit.

    The error message is expected since the usage of non-dedicated routing from an input clock pin to a PLL is not recommended . Reason is that this could introduce jitter and TimeQuest will not provide an accurate compensation delay figure.

    Related Products

    This article applies to 5 products

    Arria® V FPGAs and SoC FPGAs
    Arria® V GT FPGA
    Arria® V GX FPGA
    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA

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