APP is an adjusted peak rate at which "digital computers" perform 64-bit or larger floating point additions and multiplications. APP is expressed in Weighted TeraFLOPS (WT), in units of 10**12 adjusted floating point operations per second. Below is an outline of how the "APP" is calculated :
n number of processors in the "digital computer"
i processor number (i,....n)
ti processor cycle time (ti = 1/Fi)
Fi processor frequency
Ri peak floating point calculating rate
Wi architecture adjustment factor
1. For each processor i, determine the peak number of 64-bit or larger floating-point operations, FPOi, performed per cycle for each processor in the "digital computer".
Note: In determining FPO, include only 64-bit or larger floating point additions and/or multiplications. All floating point operations must be expressed in operations per processor cycle; operations requiring multiple cycles may be expressed in fractional results per cycle. For processors not capable of performing calculations on floating-point operands of 64-bits or more the effective calculating rate R is zero.
2. Calculate the floating point rate R for each processor
Ri = FPOi/ti.
3. Calculate APP as
APP = W1 x R1 W2 x R2 … Wn x Rn.
4. For "vector processors", Wi = 0.9. For non-"vector processors", Wi = 0.3.
The first determination an exporter must make is whether the computer is capable of performing 64-bit or larger floating-point arithmetic. If it is not, the WT value is zero.
The APP (Adjusted Peak Performance) for a single Nios II processor equals 0, since the Nios II does not have native 64-bit floating point support. However, keep in mind that the APP should be considered somewhat of a systems metric, and its value is dependent on how the overall system is designed. For example, if you create a custom instruction to add 64-bit floating point support to a single Nios II, or if you were to use multiple Nios II's on your chip to build 64-bit floating point support, or if you add multiple FPGAs to your board each with a different memory for the processors in it to create 64-bit floating point support, then, you would probably end up with a different non-zero APP value for each case. Therefore, due to the many possible variables that need to be considered in the APP calculation that are outside of Altera's direct knowledge or control, the actual APP value for an end system can only be correctly calculated and determined by the designer or user of the particular system. But for most designs solely composed of Nios II processors, the APP should usually be well below the 0.75 WT (Weighted Tera-Flops) value that the United States Department of Commerce is worried about.
For more information, refer to the "Practitioner's Guide To Adjusted Peak Performance" document, which is provided by the United States Department of Commerce Bureau of Industry and Security:
http://www.bis.doc.gov/hpcs/app-wtpractitionersguidefeb22with-cover.pdf