Article ID: 000074372 Content Type: Troubleshooting Last Reviewed: 01/04/2023

Why does the Generic Serial Flash Interface (GSFI) Intel® FPGA IP fail to write certain byte into the flash?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to the limitation in the Intel® Quartus® Prime Software version 19.1 and earlier, certain byte unable to write into the flash due to unsupported byteenable patterns/cases when the GSFI IP is connected to a 64-bit Avalon master and burst data transfer is being used.

    Below are the unsupported GSFI IP byteenable patterns/cases:

    • 4'b0110
    • 4'b0111
    • 4'b1110
    Resolution

    To work around this problem, either send data in 32-bit width or avoid using the unsupported byte enable patterns/cases.

    This problem is fixed starting with the Intel® Quartus® Prime Standard Edition Software version 20.1.

    Related Products

    This article applies to 8 products

    Intel® Arria® 10 FPGAs and SoC FPGAs
    Intel® Cyclone® 10 FPGAs
    Stratix® V FPGAs
    Arria® V FPGAs and SoC FPGAs
    Cyclone® V FPGAs and SoC FPGAs
    Cyclone® IV FPGAs
    Stratix® IV FPGAs
    Arria® II FPGAs

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