Article ID: 000074346 Content Type: Troubleshooting Last Reviewed: 03/25/2015

Why does simulation fail for the RapidIO II Megacore when using VHDL?

Environment

    Quartus® II Subscription Edition
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Description Due to a problem with the Quartus® II software, simulation will fail for the RapidIO II Megacore when the simulation model is generated using VHDL.
Resolution

You must use the Verilog simulation model.

This problem is scheduled to be fixed in a future version of the Quartus II software.

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