Article ID: 000074223 Content Type: Troubleshooting Last Reviewed: 05/01/2013

Additive Latency Not Supported for HPS Hard Memory Controller in Arria V and Cyclone V SoC Devices

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

This problem affects DDR2, DDR3, and LPDDR2 products.

Additive latency is not supported for interfaces targeting the HPS hard memory controller in Arria V or Cyclone V SoC HPS devices.

Resolution

There is no workaround for this issue.

This issue will be fixed in a future release.

Related Products

This article applies to 2 products

Cyclone® V FPGAs and SoC FPGAs
Arria® V FPGAs and SoC FPGAs

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