Article ID: 000074131 Content Type: Troubleshooting Last Reviewed: 06/10/2019

Why does Avalon-ST data pattern checker IP fail to reset all internal counters and statistics when the RST bit of counter control register is set to 1?

Environment

    Intel® Quartus® Prime Standard Edition
    Intel® Quartus® Prime Pro Edition
    Verification
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in Embedded Peripherals IP User Guide (UG-01085 | 2019.04.01), it mis-defined the RST bit counter control register as bit[8] in Table 398. Counter Control Field Descriptions.
In fact, the RST bit should be bit[1].
You can reset all counters and statistics by writing bit[1] of counter control register to 1.

Resolution

This problem is currently scheduled to be resolved in a future release of Embedded Peripherals IP User Guide.

Related Products

This article applies to 6 products

Intel® Cyclone® 10 GX FPGA
Cyclone® IV E FPGA
Intel® Stratix® 10 GX FPGA
Intel® Cyclone® 10 LP FPGA
Intel® Arria® 10 GX FPGA
Intel® Stratix® 10 TX FPGA

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