Article ID: 000074108 Content Type: Troubleshooting Last Reviewed: 09/11/2012

What's the difference when migrating PCIe designs from StratixIV to StratixV?



Figure 5-2 of the IP Compiler for PCI Express® User Guide groups signals into several categories. The following lists each category and if signals within each category have been added, removed or changed when migrating to Stratix® V devices.


Component Specific: No direct mapping, signals in this grouping have been changed or removed.


Reset and Link Training: No direct mapping of reset signals.  Some signals related to resets in this category have been added or removed.  Also, reset signal definitions may have changed.


Reconfiguration Block: This interface does not exist in StratixV devices.


Transceiver Control: Only reconfig_fromgxb and reconfig_togxb equivalent signals remain.  These two signals have been renamed to reconfig_fromxcvr and reconfig_toxrvr.


Config(Transaction Layer Configuration): Behavior of this interface has changed slightly as well as the definition of hpg_ctrler.


PIPE Interface Simulation Only:

   Non 8-bit PIPE signals: Clocking signals have been renamed and additional signals have been added.


Test Interface: The mapping and bits available for use on this interface have changed.


A complete description of the individual signal within each signal category can be found in the following User Guides:

IP Compiler for PCI Express User Guide

StratixV Hard IP for PCI Express User Guide

Related Products

This article applies to 2 products

Stratix® IV GX FPGA
Stratix® V GX FPGA